1. Field of the Invention
The present invention relates to a liquid crystal display device and a fabricating method thereof enabling to monitor an ashing rate just to carry out the process of forming a data line and source/drain electrodes uniformly using Mo.
2. Discussion of the Prior Art
Generally, a liquid crystal display has characteristics of low-voltage driving, low power consumption, full-color realization, lightness and compact size, and the like. These characteristics enable the widespread use of liquid crystal displays in devices such as televisions, airplane monitors, PDAs, mobile phones, and the like as well as calculators, watches, notebook computers, and personal computers.
Liquid crystal displays mainly include a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel. Liquid crystal panels also include first and second glass substrates bonded to each other with a space therebetween and a liquid crystal layer injected in the space between the first and second glass substrates.
On the first glass substrate (TFT array substrate), a plurality of gate lines are arranged in one direction at a predetermined distance from each other. A plurality of data lines are arranged in a direction perpendicular to the gate lines at a predetermined distance from each other. A plurality of pixel electrodes are formed in a matrix pattern in pixel areas defined at locations where the gate and data lines cross each other. A plurality of thin film transistors are switched by signals from the gate lines and transfer signals from the data lines to the pixel electrodes.
The second glass substrate (color filter substrate) supports a black matrix layer for cutting off light to areas other than the pixel areas, an R/G/B color filter layer for representing colors, and a common electrode for realizing an image.
The first and second substrates are bonded to each other by a sealant having a liquid crystal injection inlet for forming a predetermined space between the substrates. Liquid crystals are injected through the inlet between the first and second substrates.
One method of injecting the liquid crystals includes the steps of maintaining a vacuum state between the two substrates bonded to each other through the sealant and dipping the liquid crystal injection inlet in the liquid crystals so that injection between the two substrates takes place by capillary action. Once the liquid crystals are injected, the liquid crystal injection inlet is sealed using a sealing agent.
In another method of fabricating a liquid crystal display a ‘liquid crystal dropping’ process is carried out where the substrates are bonded to each other after a proper amount of liquid crystals have been dropped on the first or second substrate.
Conventionally, a thin film transistor array having the gate line, data line, pixel electrode, and thin film transistor formed on the first substrate (TFT array substrate) is fabricated using 5˜8 masks. More recently, a new fabrication technique using four masks has been developed. In the new fabrication method, a 4-mask process, is used in the four mask process, a separate mask is used for a gate line forming process, a process of forming a data line having source/drain electrodes and an active layer, a process of forming a contact hole in a passivation layer, and a process of forming a pixel electrode, respectively.
In the 4 mask process, molybdenum (Mo) is used to form the data line instead of chromium (Cr) in the process of forming the data line and active layer. In this process, however, the etch rate variation of Mo is greater than that of Cr.
A method for fabricating a thin film transistor array in a liquid crystal display using four masks according to the prior art will now be explained by referring to FIGS. 1 and 2 of the drawings.
FIG. 1 illustrates a layout of a liquid crystal display using four masks according to a prior art process. FIGS. 2A to 2G illustrate cross-sectional views of a process along cutting lines I–I′, II–II′, and III–III′ at various stages of the prior art process.
Referring to FIG. 1, a liquid crystal display by the 4-masks process includes a gate line 101 arranged in one direction and a data line 105d arranged in a direction perpendicular to the gate line 101. A pixel area is defined by the gate line 101 and the data line 105d. As will subsequently be described, a semiconductor layer 103 and a metal layer are stacked on the gate line 101.
A pixel electrode 107a is formed in the pixel area, and a thin film transistor is formed at an intersection between the gate line 101 and data line 105d. A contact hole 109a is formed at a drain electrode of the thin film transistor in order to connect the drain electrode to the pixel electrode 107a. 
Other contact holes 109b and 109c are formed on areas of a pad 101b of the gate line 101 and a pad 105c of the data line 105d just to have pad electrodes 110 formed thereon with the same material of the pixel electrode 107a, respectively.
Referring to FIG. 2A, after a substrate 100 has been cleaned, a gate metal is deposited on the substrate 100 by sputtering. A first photoresist layer is coated on the gate metal, and then exposure and development to form a first photoresist pattern P/R1. Then, the gate metal is selectively removed using the first photoresist pattern as a mask to form a gate line 101 and a gate pad 101b. The photoresist pattern P/R1 is then stripped.
Referring to FIG. 2B, a gate insulating layer 102, a semiconductor layer 103, an ohmic contact layer 104, and a data metal layer 105 having low resistance are sequentially formed on an entire surface of the substrate including the gate line and pad 101 and 101b. A second photoresist layer is then coated on the data metal layer 105. In this case, the data metal layer 105 having the low resistance is formed of Mo.
Referring to FIG. 2C, a second photoresist pattern P/R2 for a data line pattern is formed by exposure and development using a second mask (half-tone mask). In this case, the second mask (half-tone mask) is formed to cut off light corresponding to the data line completely as well as transmit the light of a predetermined quantity to a portion corresponding to a channel area of a thin film transistor. Hence, the developed second photoresist pattern maintains its originally-deposited thickness on a data line forming area but is formed relatively thin on the channel area of the thin film transistor.
Subsequently, the low-resistance data metal layer 105, ohmic contact layer 104, and semiconductor layer 103 except portions in the data line (including pad) and thin film transistor forming areas, are removed by wet or dry etching using the second photoresist pattern P/R2 as a mask.
Referring to FIG. 2D, ashing is carried out on the second photoresist pattern P/R2 in order to remove a portion of the second photoresist pattern corresponding to the channel area of the thin film transistor. In this case, an overall thickness of the second photoresist pattern is decreased as well as a width thereof. Hence, widths of the data line and the source/drain electrodes that will be formed later will be varied.
Referring to FIG. 2E, the low resistance data metal layer 105 and ohmic contact layer 104 corresponding to the channel area of the thin film transistor are etched using the ashed second photoresist pattern P/R2. The etching process forms a data line 105d including a final pad and a thin film transistor including source and drain electrodes 105a and 105b. The second photoresist pattern P/R2 is then stripped.
Referring to FIG. 2F, a passivation layer 106 is deposited over an entire surface of the substrate including the source and drain electrodes 105a and 105b. Then, a third photoresist P/R3 is coated on the passivation layer 106. The photoresits is exposed and developed to form a third photoresist pattern P/R3 exposing a portion of the drain electrode 105b and the gate and data pads 101b and 105c. The passivation layer 106 is then selectively etched using the third photoresist pattern as a mask to form contact holes 109a, 109b, and 109c on the drain electrode 105b, gate pad 101b, and data pad 105c, respectively. Then, the third photoresist pattern P/R3 is stripped.
Referring to FIG. 2G, a transparent electrode (ITO) 107 is deposited on an entire surface and connected to the drain electrode 105b, gate pad 101b, and data pad 105c through the contact holes 109a, 109b, and 109c and fourth photoresist P/R4 is coated on the transparent electrode 107. Then the photoresist is exposed and developed to form a fourth photoresist pattern P/R4 for patterning a pixel electrode and each pad electrode.
A pixel electrode 107a is formed by removing a portion of the transparent electrode selectively using the fourth photoresist pattern as a mask, and simultaneously pad electrodes 110 are formed on the pads. The fourth photoresist pattern is then stripped.
The prior art liquid crystal display and fabricating method art have the following disadvantages or problems. First, when the liquid crystal display is fabricated using the four masks, when the data metal layer and semiconductor layer are initially patterned, ashing is carried out on the photoresist. Then, the data line metal is etched again to form the final data line. Hence, if Mo is used for the data line metal, the MO etch rate varies at each location. Thus, it is difficult to provide a data line having a precise pattern. Secondly, since it is difficult to provide a precisely patterned data line, the specific resistance of the data line varies. A resistance variation in the data lines increases the possibility of failure of the liquid crystal display.